Due to continued technological innovations in the field of semiconductor fabrication that allow integrated circuits to be designed according to smaller design rules (DR), semiconductor devices are becoming more highly integrated. Typically, highly integrated circuits are designed using multi-layered metal interconnection structures in which the wires/interconnects are formed from different metals layers of an integrated circuit. Generally, multi-layered metal interconnection lines are formed of a metallic material, such as copper (Cu), having low resistivity and high reliability to yield improved performance. However, copper is difficult to pattern using a conventional photolithography/etching techniques, especially when the copper wires are formed according to relatively small design rules. Accordingly, dual damascene methods have been developed to enable formation of highly integrated copper metal interconnect structures.
In general, dual damascene methods are used to form upper metal lines that are electrically connected to lower metal lines. More specifically, a dual damascene method typically includes process steps including forming a via hole and a trench region in an interlayer dielectric (ILD) layer formed over a lower metal line. The via hole is formed in the ILD layer in alignment with a predetermined region of the lower metal line, and the trench region is formed to have a line-shaped groove that crosses over the via hole. Typically, a thin etch stop layer is formed between the lower metal line layer of a substrate and the ILD layer as a means for protecting the lower metal line. The upper metal lines and contacts are formed by filling the via hole and a trench region in the ILD layer with conductive material (such as copper). The conductive material in the via hole forms a via contact between the lower metal line and the upper metal line formed by the conductive material filling the trench region.
Although dual damascene methods allow formation of metal interconnect structures that yield improved performance, such methods become more problematic with decreasing design rules. For instance, with decreasing design rules, parasitic resistance and capacitance that exists between adjacent metal wiring layers in a lateral direction or in a vertical direction may affect the performance of the semiconductor devices. Such parasitic resistance and capacitance components in a metal wiring layer generally cause a decrease in the operating speed, and thus deteriorate the electrical characteristics of the device. Further, the parasitic resistance and capacitance components increase the total power consumption of chips in the semiconductor device and an amount of signal leakage.
To address these issues, interlayer dielectric material having low dielectric constants have been used to reduce parasitic capacitances. Moreover, to decrease capacitance, the ESL (etch stop layer) between the lower metal line and ILD layer is formed as thin as possible. However, even when the ILD layer is selected to have an etching selectivity to the etch stop layer, when forming the via hole in the ILD layer, the portion of the etch stop layer that is exposed through the via hole can be etched such that the lower metal line is exposed to the etching atmosphere. The exposure of the lower metal line to an etching atmosphere can result in certain defects such as formation of black vias (which are recesses formed in exposed surface of lower metal line) or copper lifting. Moreover, during a subsequent ashing process to remove a photoresist pattern, the exposed surface of the lower metal line may react with oxygen and form a metal oxide layer. Such oxidation increases the electrical resistance of the metal interconnect structure and may result a defective contact between the via and lower metal line due to a lifting phenomenon.